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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Model-specific register</span></span>
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</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="Machine_state_register" title="Machine state register">Machine state register</a>.</div>
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<p>A <b>model-specific register</b> (<b>MSR</b>) is any of various <a href="Control_register" title="Control register">control registers</a> in the <a href="X86" title="X86">x86</a> <a href="System_architecture" class="mw-redirect" title="System architecture">system architecture</a> used for <a href="Debugging" title="Debugging">debugging</a>, program execution tracing, <a href="Computer_performance" title="Computer performance">performance</a> monitoring, and toggling certain <a href="CPU" class="mw-redirect" title="CPU">CPU</a> features.
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<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>
<p>With the introduction of the <a href="80386" class="mw-redirect" title="80386">80386</a> processor, <a href="Intel" title="Intel">Intel</a> began introducing "experimental" features that would not necessarily be present in future versions of the processor. The first of these were two "test registers" (TR6 and TR7) that enabled testing of the processor's <a href="Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffer</a> (TLB); a special variant of the <style data-mw-deduplicate="TemplateStyles:r886049734">
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</style><span class="monospaced">MOV</span> instruction allowed moving to and from the test registers.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Three additional test registers followed in the 80486 (TR3–TR5) that enabled testing of the processor's caches for code and data.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> None of these five registers were implemented in the subsequent Pentium processor; the special variant of <span class="monospaced">MOV</span> generated an invalid <a href="Opcode" title="Opcode">opcode</a> exception.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>
</p><p>With the introduction of the <a href="Pentium_(original)" title="Pentium (original)">Pentium</a> processor, Intel provided a pair of instructions (<span class="monospaced">RDMSR</span> and <span class="monospaced">WRMSR</span>) to access current and future "model-specific registers", as well as the <span class="monospaced"><a href="CPUID" title="CPUID">CPUID</a></span> instruction to determine which features are present on a particular model. Many of these registers have proven useful enough to be retained. Intel has classified these as <i>architectural</i> model-specific registers and has committed to their inclusion in future product lines.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>
</p><p>On modern x86-based systems, the <a href="BIOS" title="BIOS">BIOS</a> or <a href="UEFI" title="UEFI">UEFI</a> firmware will initialize <a href="CPUID" title="CPUID">CPUID</a> registers and model-specific registers on each system startup.
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<div class="mw-heading mw-heading2"><h2 id="Using_MSRs">Using MSRs</h2></div>
<p>Reading and writing to these registers is handled by the <code>rdmsr</code> and <code>wrmsr</code> instructions, respectively. As these are <a href="Privilege_(computing)" title="Privilege (computing)">privileged</a> instructions, they can be executed only by the operating system. Use of the Linux <i>msr</i> kernel module creates a pseudo file "/dev/cpu/<i>x</i>/msr" (with a unique <i>x</i> for each processor or processor core). A user with permissions to read and/or write to this file can use the file I/O API to access these registers. The <i>msr-tools</i><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> package provides a reference implementation.
</p><p>Documentation regarding which MSRs a certain processor implementation supports is usually found in the processor documentation of the CPU vendor. Examples for rather well-known MSRs are the <a href="Memory_type_range_register" title="Memory type range register">memory type range registers</a> (MTRRs) and the <a href="Address-range_register" title="Address-range register">address-range registers</a> (ARRs).
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<div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2></div>
<ul><li><a href="LOADALL" title="LOADALL">LOADALL</a></li></ul>
<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">
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</style><cite class="citation book cs1">"10.6.2 Test Registers". <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/intel/80386/230985-001_80386_Programmers_Reference_Manual_1986.pdf"><i>80386 PROGRAMMER'S REFERENCE MANUAL</i></a> <span class="cs1-format">(PDF)</span>. <a href="Intel" title="Intel">Intel</a>. 1986.</cite></span>
</li>
<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite class="citation book cs1">"10.6.2 Test Registers". <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/intel/80486/i486_Processor_Programmers_Reference_Manual_1990.pdf"><i>i486 PROCESSOR PROGRAMMER'S REFERENCE MANUAL</i></a> <span class="cs1-format">(PDF)</span>. <a href="Intel" title="Intel">Intel</a>. 1990.</cite></span>
</li>
<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><cite class="citation book cs1">"23.2.12 Test Registers". <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/intel/pentium/1993_Intel_Pentium_Processor_Users_Manual_Volume_3.pdf"><i>Pentium Processor User's Manual Volume 3: Architecture and Programming Manual</i></a> <span class="cs1-format">(PDF)</span>. <a href="Intel" title="Intel">Intel</a>. 1993.</cite></span>
</li>
<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><cite id="CITEREFAlan_Cruse" class="citation web cs1">Alan Cruse. <a rel="nofollow" class="external text" href="https://www.cs.usfca.edu/~cruse/cs630f06/lesson27.ppt">"Model-Specific Registers"</a> <span class="cs1-format">(PPT)</span>. <i>Lecture notes, Advanced Microcomputer Programming class, University of San Francisco, 2006</i>.</cite></span>
</li>
<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><cite class="citation book cs1">"2.1 ARCHITECTURAL MSRS". <a rel="nofollow" class="external text" href="https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-4-model-specific-registers.html"><i>Intel 64 and IA-32 Architectures Software Developer's Manual Volume 4: Model-Specific Registers</i></a>. <a href="Intel" title="Intel">Intel</a>. May 2020.</cite></span>
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<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://01.org/msr-tools">msr-tools</a> at 01.org</span>
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<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>
<ul><li><a rel="nofollow" class="external free" href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/reading-writing-msrs-in-linux.html">https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/reading-writing-msrs-in-linux.html</a></li></ul>
<ul><li>The Intel Model-Specific Registers (MSRs) are described in-depth in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4; the link to the Intel reference manuals (PDFs) download page (which includes Vol 4):</li></ul>
<p><a rel="nofollow" class="external free" href="https://cdrdv2.intel.com/v1/dl/getContent/671200">https://cdrdv2.intel.com/v1/dl/getContent/671200</a>
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